This invention is applicable to data processing systems with multi-level memory where the second level (L2) memory used for both unified (code and instructions) level two cache and flat (L2SRAM) memory used to hold critical data and instructions. The second level memory (L2) is used for multiple purposes including unified instruction and data level two cache, directly addressable SRAM memory used to hold critical data and code accessible by both external and internal direct memory access (DMA) units.
When the level one data cache controller is granted access to the level one data cache, this access could force an existing line to be evicted. The CPU can also force the level one data cache to evict lines though the block writeback operation. At the same time, the level two cache could be receiving a DMA access to the same line. This situation could break coherency, if DMA data were committed incorrectly. This could occur by writing to the level two memory then overwriting that data with the level one cache victim. This could also occur by sending the DMA data as a snoop write to the level one data cache. This forces the level one data cache to write the DMA data to its cache after the victim has been evicted. This effectively, drops the DMA write. Thus when a victim is in progress, a DMA write sent as snoop could miss the victim.
Hardware managed cache coherence can greatly simplify the programming model for multi-core systems with many caching masters. The coherence hardware ensures ordered handoffs of concurrently accessed cache blocks to make sure all masters see the same update order (true sharing) and/or don't interfere with each other's data accidentally (false sharing). While simplifying the programming model, adding this hardware can contribute complexity and performance loss in many ways. Additional coherence hardware could increase request latency through stalls needed to enforce correct ordering. Additional coherence hardware could cause loss of bandwidth between all masters and endpoints because of stalls. Such additional coherence hardware could contribute to added hardware complexity.